Chips to Startup: EDA tools in 315 institutions; ISM 2.0 to expand to 500
Union Minister Ashwini Vaishnaw said on 7 March 2026 that India has made significant progress in four years towards the Chips to Startup (C2S) target of training 85,000 semiconductor engineers in 10 years.
Summary
Union Electronics and IT Minister Ashwini Vaishnaw said on 7 March 2026 that the Chips to Startup (C2S) initiative of the India Semiconductor Mission has made significant progress in four years towards its 10-year target of training 85,000 engineers in semiconductor design. Electronic Design Automation (EDA) tools supported by Synopsys, Cadence, Siemens, Renesas, Ansys and AMD are available in 315 academic institutions, and chips designed by students are fabricated and tested at the Semiconductor Laboratory (SCL), Mohali. PIB described it as the world's largest open-access EDA programme, with over 1.85 crore hours of tool use. Under India Semiconductor Mission 2.0 the scheme is to be expanded to 500 institutions.
Key facts
- Date
- 7 March 2026
- Programme
- Chips to Startup (C2S), India Semiconductor Mission
- Target
- 85,000 engineers in 10 years
- Institutions
- 315 now; 500 under ISM 2.0
- EDA use
- Over 1.85 crore hours
- Fabrication
- Semiconductor Laboratory (SCL), Mohali
Practice MCQs 2 questions
Under the Chips to Startup (C2S) programme, what is the target for training semiconductor engineers over 10 years?
Show answer
Correct answer: C — 85,000
The C2S programme aims to train 85,000 engineers in semiconductor design over 10 years.
Consider the following statements about the Chips to Startup (C2S) programme: 1. Chips designed by students are fabricated and tested at the Semiconductor Laboratory (SCL), Mohali. 2. Under India Semiconductor Mission 2.0, the programme is to be expanded to 500 academic institutions. Which of the above is/are correct?
Show answer
Correct answer: C — Both 1 and 2
Both are correct: student chips are made at SCL Mohali, and ISM 2.0 will take the programme from 315 to 500 institutions.